Automatic test pattern generation (“ATPG”) was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically.
Generally, when an ATPG tool generates a scan test pattern for a fault, or a set of faults, only a small percentage of scan cells in the scan channels need to take specific values (e.g., care bits). The rest of the cells in the scan channel are “don't care”, and are usually filled with random values. Relatively few bits are “care” bits.
Test Compression is a technique used as part of a Design For Test (“DFT”) method to reduce the time and cost of testing integrated circuits. Straightforward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements. Test Compression takes advantage of the small number of significant values (care bits) techniques to reduce test data and test time, by decompressing the scan input on chip and compressing the test output. This technique allows highly compressed test stimuli to be applied from low-pin count testers and compressed test responses to be measured.
Scan channels are typically loaded by shifting them into the design registers 1 bit per clock cycle and thus, the longer the scan channels the more time it takes to load. The loading and unloading of long scan channels is not a very efficient use of tester time. A Test decompressor allows compressed test stimuli to be loaded from a small number of tester pins to a large number of very short internal scan channels; thereby reducing the test loading time. On the output side the short scan channels feeding a test compressor can reduce the time taken to unload the test response and store it on the tester for comparison.
However, as Test Compression decreases channel lengths, the number of specified bits (e.g., care bits) per time slice increases. Further, at higher compression ratios, because the channel length is decreasing, the total number of variables (e.g., scan data) and, hence, the total number of care bits that can fit into a test pattern, are reduced. In addition, there can be a large variance in the number of care bits across time slices.
XOR decompressors (e.g., a linear spreader network of a plurality of XOR logic gates) are limited in that they are restricted to using only the scan data available in the same scan cycle. This places an upper bound on the number of care bits that are in the same scan cycle. This also leads to inefficiencies. For ample, if the ATPG generated test does not require any care bits or requires very few care bits in a test slice, the slack (e.g., unused scan data) cannot be re-used for a different scan cycle that has more care bits.
Sequential decompressors overcome the above-discussed inefficiencies of the XOR decompressors by solving the linear equations of the entire test pattern simultaneously instead of slice-by-slice. Specifically, each equation of the system of equations corresponds to a channel bit associated with a care bit. Scan data is reused among multiple test slices, so that scan data from test slices having fewer care bits can be utilized in solving for test slices with more care bits. However, sequential decompressors are still limited by the size of a scan cube (which includes, among other things, a number of scan slices). In other words, even though the scan data from the scan cube is used more efficiently, the total amount of information (e.g., scan data) in the scan cube is still the same. For example, the total number of bits for each ATPG test would be the length of the channel (L) multiplied by the number of scan-in inputs (M) (i.e., L*M). Thus, with the current solutions, sequential decompressors are limited to solving up to L*M number of care bits. In other words, faults requiring less than L*M care bits are potentially solvable; however, if the fault requires more care bits than the L*M value, then that fault will most likely be undetectable. For example, if only 250 bits of scan data are brought in, and the fault requires 500 care bits to detect the fault, then that fault will most likely not be detected. Therefore, as the channel length decreases, the likelihood of solving for substantially all of the faults in the circuit also decreases.
Further, as the channel length L decreases, the number of faults that can be detected per test pattern also decreases. For example, assuming the scan data from above, if multiple faults each require care bits in the range of 50-60 bits, which, individually, should generally be solvable, the probability of these faults conflicting is increased. Two or more faults are deemed to conflict when the two or more faults require conflicting values at the exact same bit position. For example, one fault might require the care bit hold a “1” at a certain bit position while another fault requires the care bit hold a “0” at the bit position. Therefore, if two faults conflict, the conflicting faults cannot be solved for with a single test pattern. Thus, additional test patterns are required to test for one of the conflicted faults. Accordingly, as the number of required test patterns increases, the test time and total data volume also increases, defeating one of the primary motivations for test compression, i.e., decreasing test time and total data volume.
Further, sequential decompressors are also limited in that the initial test slices (e.g., the test slice closer to the scan out) for the sequential decompressor will have equations comprising only the starting state values of a linear feedback shift register (“LFSR”) (also referred to as a Pseudo-Random Pattern Generator—PRPG) utilized in the sequential decompression. Accordingly, any care bits in these bit positions will likely not be solved. Traditionally, to overcome the aforementioned starting-state problem of the PRPG, the PRPG was loaded with scan input variables before any values were shifted into the scan channels. However, this required that the channels be frozen while the scan input variables were being loaded into the PRPG (e.g., by holding the channels' clocks constant), which required an additional test control pin or other internal hardware to achieve.
Accordingly, there is a need for an efficient method and system of bringing additional variables from a scan cube, as desired, for certain test patterns without simultaneously increasing the length of the scan channels.
Further, there is also a need for an efficient method of bringing additional variables into the PRPG in the early cycles of the ATPG process without utilizing any additional hardware or control pins.